The self aligned Silicide (or Salicide) process is known in CMOS technology to create thin films of low resistivity. As the device dimensions shrink, the area of diffused regions shrink accordingly, and the parasitic resistance (to lateral conduction) of the conductive film is increased. This adversely affects the device operation because of the increased heat dissipation and increased time delay of signal propagation.
Due to its low bulk resistivity, titanium silicide (TiSi2) is an attractive material for lowering the sheet resistivity so that diffused regions can be connected over longer distances without additional heat dissipation.
However, the Schottky barrier height in these processes is not well controlled. It would be very desirable to control the barrier height of a titanium silicide Schottky device with a simple process.